1. Field of the Invention
The present invention relates to telecommunications systems and, in particular, to a second-order phase locked loop (PLL) synchronizer circuit that adapts to carrier regeneration and baseband data timing recovery circuits in modem applications.
2. Discussion of the Prior Art
A basic digital communication system transmits information over a communications channel between a source and a destination which are physically separated from one another.
Communications channels designed to handle voice transmissions (i.e., the telephone network) have inherent characteristics which make it difficult for them to be used to transmit binary bit streams. Therefore, to permit the transmission of digital data over voice channels, it is necessary to convert the digital data at the transmission point into a signal which is compatible with the voice channel. This is done by utilizing the digital data to modulate a carrier waveform which is within the voice frequency range, transmitting the modulated signal, and then demodulating the signal at the receiver to separate the transmitted data from the modulated carrier waveform.
Data communications systems that operate at high data transmission rates, i.e. 1200 baud or more, typically use a modulation technique know as phase shift keying (PSK) modulation.
A 2-phase PSK system uses one phase of the carrier frequency for one binary state and the other phase for the other binary state. The two phases are 180.degree. apart and are detected by a synchronous detector using a reference signal at the receiver which is of known phase with respect to the incoming signal. This known signal is at the same frequency as the incoming signal carrier and is arranged to be in phase with one of the binary signals.
In a relative phase PSK system, a binary "1" is represented by sending a signal burst of the same phase as that of the previous signal burst. A binary "0" is represented by a signal burst of a phase opposite that of the previously transmitted signal. The signals are demodulated at the receiver by integrating and storing each signal burst for one bit period for phase comparison with the next signal burst.
In a quadrature or 4-phase PSK system, two binary channels are phase multiplexed onto one tone by placing them in phase quadrature. In 4-phase PSK, one of four possible waveforms is transmitted during each signalling interval. These waveforms correspond to phase shifts of 0.degree., 90.degree., 180.degree. and 270.degree.. The receiver utilizes two local reference waveforms derived from a coherent local carrier to demodulate the signals.
Quadrature phase shift keying schemes provide the best tradeoff between power and band width requirements.
However, to accurately demodulate an incoming PSK signal, the output of the receiving filter must be sampled at precise sampling instants. To do this sampling requires a receiver clock signal that is synchronized with the transmitter clock signal. Lack of synchronization will result in signal distortion.
There are three general ways of obtaining this synchronization. According to a first method, the clock information can be derived from a primary or secondary standard; for example, the transmitter and receiver can be controlled from the same master clock. A second method utilizes a transmitted synchronizing clock signal. According to a third method, the clock signal is derived from the received waveform itself.
The first method mentioned above is used most often in large data communications networks. However, the high cost of this method does not justify its use in point-to-point systems with low transmission rates. The second method involves the transmission of a clock signal along with the data which means that a portion of the transmission capacity is devoted to the clock signal; this presents problems if the available capacity is small compared to the data rate requirements. The third method, self-synchronization, is a very efficient method of synchronizing the receiver to the transmitter. Self-synchronization methods extract a local carrier reference as well as timing information from the received waveforms. Many conventional self-synchronizing circuits make use of a phase locked loop (PLL) for extracting the correct phase and frequency of the carrier waveform.
However, presently-available analog PLL-demodulators typically require tweaking. Furthermore, it is not easy to change their operating frequency. Low pass filters are required to remove input glitches and high order harmonics at the demodulator outputs. System parameters are not easily changed. These devices rely upon an analog level comparator to differentiate the phase angle of the incoming signal. The demodulated signal transmissions are not clearly defined. These devices incorporate no error correcting features.
Conventional digital signal demodulators require A/D and D/A converters resulting in a slow speed system which is implemented only at very high cost.